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rev 1.1 - 5/01/98 1 preliminary 1 2 3 4 5 6 7 8 9 10 11 12 3.3v 64k x 32 fast cmos synchronous static ram with burst counter features n interfaces directly with the x86, pentium, 680x0 and powerpc processors n single 3.3v power supply n mode selectable for interleaved or linear burst: interleaved for x86 and pentium linear for 680x0 and powerpc n fast access times: 9, 10, 12 and 15 ns n high-density 64k x 32 architecture with burst address counter n fully registered inputs n high-output drive: 30 pf at rated t a n asynchronous output enable n self-timed write cycle n separate byte write enables and one global write enable n internal burst read/write address counter n internal registers for address, data, controls n burst mode selectable n sleep mode n packages: 100-pin qfp - (q) 100-pin tqfp - (tq) description the pdm34089 is a 2,097,152 bit synchronous ran- dom access memory organized as 65,536 x 32 bits. it is designed with burst mode capability and interface controls to provide high-performance in second level cache designs for x86, pentium, 680x0, and powerpc microprocessors. addresses, write data and all control signals except output enable are con- trolled through positive edge-triggered registers. write cycles are self-timed and are also initiated by the rising edge of the clock. controls are provided to allow burst reads and writes of up to four words in length. a 2-bit burst address counter controls the two least-signi?ant bits of the address during burst reads and writes. the burst address counter selec- tively uses the 2-bit counting scheme required by the x86 and pentium or 680x0 and powerpc micropro- cessors as controlled by the mode pin. individual write strobes provide byte write for the four 8-bit bytes of data. an asynchronous output enable sim- pli?s interface to high-speed buses. pdm34089 tm i486, pentium are trademarks of intel corp. powerpc is a trademark of the international business machines corporation.
pdm34089 2 rev 1.1 - 5/01/98 preliminary functional block diagram 32k x 32 memory array input registers address register burst counter and logic byte 4 write driver byte 3 write driver byte 2 write driver byte 1 write driver byte 1 write register byte 2 write register byte 3 write register byte 4 write register enable register clr q1 q0 a15-a0 mode adv clk bw1 bw2 bw3 bw4 bwe ce ce2 ce2 oe gw adsp adsc 16 8 8 dq32-dq1 16 14 16 8 8 8 8 8 32 32 8 a1,a0 a0' a1' output buffer
pdm34089 rev 1.1 - 5/01/98 3 preliminary 1 2 3 4 5 6 7 8 9 10 11 12 nc dq16 dq15 v ccq v ssq dq14 dq13 dq12 dq11 v ssq v ccq dq10 dq9 v ss nc v cc zz dq8 dq7 v ccq v ssq dq6 dq5 dq4 dq3 v ssq v ccq dq2 dq1 nc a6 a7 ce ce2 bw4 bw3 bw2 bw1 ce2 v cc v ss clk gw bwe oe adsc adsp adv a8 a9 nc dq17 dq18 v ccq v ssq dq19 dq20 dq21 dq22 v ssq v ccq dq23 dq24 ft v cc nc v ss dq25 dq26 v ccq v ssq dq27 dq28 dq29 dq30 v ssq v ccq dq31 dq32 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a5 a4 a3 a2 a1 a0 nc nc v ss v cc nc nc a10 a11 a12 a13 a14 a15 nc 46 47 48 49 50 pdm34089 pinout
pdm34089 4 rev 1.1 - 5/01/98 preliminary pinout note: 1.mode and ft are dc operated pins. do not alter input state while device is operating. name i/o description name i/o description a14-a2 i address inputs a14-a2 ce , ce2, ce2 i chip enables a1, a0 i address inputs a1 & a0 bwe i byte write enable dq1-dq32 i/o read/write data bw1 - bw4 i byte write enables nc no connect oe i output enable mode (1) i burst sequence select clk i clock adv i burst counter advance zz i sleep mode adsc i controller address status v cc power supply (+3.3v) adsp i processor address status v ccq output power for dq? (+3.3v 5%) gw i global write v ss array ground ft (1) i must be tied low for proper operation v ssq output ground for dq? burst sequence table burst sequence interleaved (1) mode = nc or v cc linear (2) mode = v ss external address a15-a2, a1, a0 a15-a2,0,0 a15-a2,0,1 a15-a2,1,0 a15-a2,1,1 1st burst address a15-a2, a1, a0 a15-a2,0,1 a15-a2,1,0 a15-a2,1,1 a15-a2,0,0 2nd burst address a15-a2, a1 , a0 a15-a2,1,0 a15-a2,1,1 a15-a2,0,0 a15-a2,0,1 3rd burst address a15-a2, a1 , a0 a15-a2,1,1 a15-a2,0,0 a15-a2,0,1 a15-a2,1,0 asynchronous truth table note: 1. l = low, h = high, x = don? care. 2. for a write operation following a read operation, oe must be high before the input data required setup time and held high through the input data hold time. 3. this device contains circuitry that will ensure the outputs will be in high-z during powerup. operation zz oe i/o status read l l data out read l h high-z write l x high-z: write data in deselected l x high-z sleep h x high-z partial truth table for writes note: 1. l = low, h = high, x = don? care. 2. using bwe and bw1 through bw4 , any one or more bytes may be written. gw bwe bw1 bw2 bw3 bw4 function hhxxxx read h l hhhh read h l l h h h write byte 1 hl llll write all bytes l x xxxx write all bytes note: 1. interleaved = x86 and pentium. 2. linear = 680x0 and powerpc compatible.
pdm34089 rev 1.1 - 5/01/98 5 preliminary 1 2 3 4 5 6 7 8 9 10 11 12 synchronous truth table (see notes 1 through 3) notes: 1. x = don? care, h = logic high, l = logic low, bwx = any one or more byte write enable signals (bw1 , bw2 , bw3 , bw4 ) and bwe are low, or gw is low. 2. bw1 enables bwx to byte 1 (dq1-dq8). bw2 enables bwx to byte 2 (dq9-dq16). bw3 enables bwx to byte 3 (dq17-dq24), bw4 enables bwx to byte 4 (dq25-dq32). 3. ad v must always be high at the rising edge of the ?st clock after an adsp cycle is initiated if a write cycle is desired (to ensure use of correct address). ce ce2 ce2 adsp adsc adv bwx clk address operation hxx x l x x - n/a deselected lxl l x x x - n/a deselected lhx l x x x - n/a deselected lxl h l x x - n/a deselected lhx h l x x - n/a deselected llh l x x x - external read cycle, begin burst llh h l x x - external read cycle, begin burst xxx h h l h - next read cycle, continue burst hxx x h l h - next read cycle, continue burst xxx h h h h - current read cycle, suspend burst hxx x h h h - current read cycle, suspend burst llh h l x l - external write cycle, begin burst xxx h h l l - next write cycle, continue burst hxx x h l l - next write cycle, continue burst xxx h h h l - current write cycle, suspend burst hxx h h h l - current write cycle, suspend burst
pdm34089 6 rev 1.1 - 5/01/98 preliminary burst mode operation this is a synchronous part. all activities are initiated by the positive, low-to-high edge of the clock (clk). this part can perform burst reads and writes with burst lengths of up to four words. the four-word burst is created by using a burst counter to drive the two least-signi?ant bits of the internal ram address. the burst counter is loaded at the start of the burst and is incremented for each word of the burst. the sequence is given in the burst sequence table. burst transfers are initiated by the adsc or adsp signals. when the adsp and ce signals are sampled low, a read cycle is started (independent of bw1 , bw2 , bw3 or bw4 ; bwe , gw and adsc ), and prior burst activity is terminated. adsp is gated by ce , so both must be active for adsp to load the address register and to initiate a read cycle. the address and the chip enable input (ce ) are sampled by the same edge that samples adsp . read data is valid at the output after the speci?d delay from the clock edge. when adsc is sampled low and adsp is sampled high, a read or write cycle is started depending on the state of bw1 , bw2 , bw3 or bw4 ; bwe , and gw . if bw1 , bw2 , bw3 , bw4 , bwe , and gw are all sampled high, a read cycle is started, as described above. if bw1 , bw2 , bw3 , or bw4 ; bwe , and gw is sampled low, a write cycle is begun. the address, write data, and the chip enable inputs (ce , ce2 and ce2 ) are sampled by the same edge that samples adsc and bw1 bw4 , bwe and gw . the adv line is held high for this clock edge to maintain the correct address for the internal write operation which will follow this second clock edge. after the ?st cycle of the write burst, the state of bw1 -bw4 , bwe and gw determines whether the next cycle is a read or write cycle, and adv controls the advance of the address counter. the adv signal advances the address counter. this increments the address to the next available ram address. you write the next word in the burst by taking adv low and presenting the write data at the positive edge of the clock. if adv is sampled low, the burst counter advances and the write data (which is sampled by the same clock) is written into the internal ram during the time following the clock edge. absolute maximum ratings note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. symbol rating coml. unit v term terminal voltage with respect to v ss ?.5 to +4.6 v t a operating temperature 0 to +70 c t bias temperature under bias ?5 to +125 c t stg storage temperature ?5 to +125 c i out dc output current 100 ma recommended dc operating conditions symbol description min. typ. max. unit v cc supply voltage 3.1 3.3 3.6 v v ccq supply voltage 3.1 3.3 3.6 v v ss supply voltage 0 0 0 v commercial ambient temperature 0 25 70 c
pdm34089 rev 1.1 - 5/01/98 7 preliminary 1 2 3 4 5 6 7 8 9 10 11 12 dc electrical characteristics (v cc = 3.3v 0.3v, all temperature ranges) notes: 1. undershoots to ?.0 for 10 ns are allowed once per cycle. 2. mode, ft and zz pins have an internal pullup and exhibit an input leakage current of 400 m a. power supply characteristics symbol description test conditions min. max. unit |i li | input leakage current v in = 0v to v cc ? 2 m a |i lo | output leakage current outputs disabled, v i/o = 0v to v cc ? 2 m a v ol output low voltage v cc = min., i ol = 8 ma 0.4 v v oh output high voltage v cc = min., i oh = ? ma 2.4 v v ih input high voltage 2.0 3.6 v v il input low voltage (1) ?.3 0.8 v symbol description test conditions -7 ns -10 ns -12 ns -15 ns unit i cc active supply current device deselected v in v il or 3 v ih, i i/o = 0 315 230 210 190 ma i sb standby current: device deselected v in v il or 3 v ih, 0 mhz all inputs static 25 20 20 20 ma i sb1 standby current: device deselected v in 0.2v or 3 v cc ?0.2v all inputs static, 0 mhz 5333ma i sb2 standby current: device deselected v in v il or 3 v ih, all inputs static 55 45 40 35 ma i sb3 sleep mode standby current: device deselected zz 3 v ccq ?0.2v 5333ma
pdm34089 8 rev 1.1 - 5/01/98 preliminary capacitance (t a = +25 c, f = 1.0 mhz) notes: 1. characterized values, not currently tested. symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 8 pf ac test conditions input pulse levels v ss to 3.0v input rise and fall times 1.5 ns input timing reference levels 1.5v output reference levels 1.5v output load see figures 1 and 2 50 w z out = 50 w v l = 1.5v i/o 30 pf 351 w 317 w 5 pf* +3.3v data out figure 1. output load figure 2. output load t cq , t olz , t ohz , t cz
pdm34089 rev 1.1 - 5/01/98 9 preliminary 1 2 3 4 5 6 7 8 9 10 11 12 ac electrical characteristics parameter symbol -7 ns -10 ns -12 ns -15 ns type units cycle time t cyc 12 16.7 20 25 min. ns clock access time (0 pf load) t cq0 8.5 9 11 13 max. ns clock to output valid (std. load) t cq 9 10 12 14 max. ns clock to output invalid t cqx 3 2 2 2 min. ns clock to output high-z t chz 5 2 2 2 min. ns 12 16.7 20 25 max. clock pulse width high t ch 4.5 6 6 6 min. ns clock pulse width low t cl 4.5 6 6 6 min. ns oe to output valid t oe 5 6 6 6 min. ns oe to output low-z t olz 0 0 0 0 min. ns oe to output high-z t ohz 5 6 6 6 max. ns zz standby time t zzs 100 100 100 100 max. ns zz recovery time t zzrec 100 100 100 100 min. ns setup times address t as 2.5 2.5 3 3 min. ns address status (adsc , adsp )t aas 2.5 2.5 3 3 min. ns address advance setup (adv )t aas 2.5 2.5 3 3 min. ns write signals (bwx , gw )t ws 2.5 2.5 3 3 min. ns data in t ds 2.5 2.5 3 3 min. ns chip enables (ce , ce2 , ce2) t ces 2.5 2.5 3 3 min. ns hold times address t ah 0.5 0.5 0.5 0.5 min. ns address status (adsc , dsp )t adsh 0.5 0.5 0.5 0.5 min. ns address advance (adv )t aah 0.5 0.5 0.5 0.5 min. ns write eignals (bwx , gw )t wh 0.5 0.5 0.5 0.5 min. ns data in t dh 0.5 0.5 0.5 0.5 min. ns chip enables (ce , ce2 , ce2) t ceh 0.5 0.5 0.5 0.5 min. ns
pdm34089 10 rev 1.1 - 5/01/98 preliminary adsp read timing diagram note: 1. e is low when ce = low, ce2 = high and ce2 = low. e is high otherwise. clk adsp valid address a0-a14 read data dq1-dq32 dqp1-dqp4 adv t cyc t w t w oe t oe valid t s t h e t olz valid t dc1, t dc2 t cd valid a 1 ,a 0 t s t h t ohz adsc a 1 ,a 0 a 1 ,a 0 a 1 ,a 0 valid bwe, gw bw1-bw4
pdm34089 rev 1.1 - 5/01/98 11 preliminary 1 2 3 4 5 6 7 8 9 10 11 12 adsp write timing diagram notes: 1. e is low when ce = low, ce2 = high and ce2 = low. e is high otherwise. 2. bwx and gw are ignored for the ?st cycle when adsp initiates the burst. adsp active loads a new address into the address- counter and forces the ?st cycle to be a read cycle. 3. oe is high before data input setup. clk adsp valid address a0-a14 t cyc t w t w t s t h e adsc adv write data dq1-dq32 dqp1-dqp4 a 1 , a 0 t s t h valid valid valid valid oe a 1 , a 0 a 1 , a 0 a 1 , a 0 bwe, gw bw1-bw4
pdm34089 12 rev 1.1 - 5/01/98 preliminary adsc read timing diagram notes: 1. 1. e is low when ce = low, ce2 = high and ce2 = low. e is high otherwise. clk adsp valid address a0-a14 read data dq1-dq32 dqp1-dqp4 adv t cyc t w t w oe t oe valid bwe, gw bw1-bw4 t s t h e t olz valid t dc1, t dc2 t cd valid valid a 1 ,a 0 t s t h t ohz adsc a 1 ,a 0 a 1 ,a 0 a 1 ,a 0
pdm34089 rev 1.1 - 5/01/98 13 preliminary 1 2 3 4 5 6 7 8 9 10 11 12 adsp write timing diagram notes: 1. e is low when ce = low, ce2 = high and ce2 = low. e is high otherwise. 2. bwx and gw are ignored for the ?st cycle when adsp initiates the burst. adsp active loads a new address into the address counter and forces the ?st cycle to be a read cycle. 3. oe is high before data input setup. clk adsp valid address a0-a14 t cyc t w t w t s t h e adsc write data dq1-dq32 dqp1-dqp4 adv valid a 1 ,a 0 t s t h valid valid valid oe valid next burst valid a 1 ,a 0 a 1 ,a 0 a 1 ,a 0 bwe, gw bw1-bw4
pdm34089 14 rev 1.1 - 5/01/98 preliminary sleep mode timing diagram notes: 1. data retention is guaranteed when zz is asserted and clock remains active. 2. adsc and adsp must not be asserted for at least 100 ns after leaving zz state. sequential non-burst read and write timing diagram notes: 1. adsp = high, adsc = low, ad v = high, ce1 = low. 2. h 3 v ih , l v il . clk snooze adsp adsc zz t zzs t zzrec clk adsp adsc adv addr ce1 oe we dq abc reads writes q(a) q(b) q(c) q(d) efg d h q(e) q(f) q(g) q(h)
pdm34089 rev 1.1 - 5/01/98 15 preliminary 1 2 3 4 5 6 7 8 9 10 11 12 ordering information device type power speed package type process temp. range preferred shipping container commercial (0 to +70 c) industrial (?0 c to +85 c) 7 commercial only 10 commercial only 12 commerical only 15 commercial only sa /s standard power blank i a automotive ( ?0 c to +105 c) blank tubes tr tape & reel ty tray pdm34089 - (64kx32) sync. static ram xxxxx x xx x x x q 100-pin qfp tq 100-pin tqfp faster memories for a faster world

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